1. Field of the Invention
This invention relates to single and multiphase phase locked loop circuits in which the phase error between a source signal and a digitally synthesized reference signal is integrated and applied to a voltage controlled oscillator which shifts the phase of the digitally synthesized reference signal to reduce the phase error signal to zero when the synthesized reference signal has a predetermined phase relationship to the source. More particularly, the invention relates to such phase locked loop circuits incorporating a sliding window averager for improved stability and response time.
2. Background Information
Control and monitoring circuits for many power electronic applications require timing reference signals that are precisely locked to the fundamental component of the source. Phase locked loop circuits have been developed which generate such timing reference signals. The heart of these phase locked loop circuits is a phase comparator and a voltage controlled oscillator (VCO). The phase comparator compares the source signal with a synthesized reference signal to generate a phase error signal which is integrated and applied to the voltage controlled oscillator to generate a signal having a frequency which varies with the phase error. This variable frequency signal is then used to shift the phase of a synthesized reference signal to drive the phase error signal to zero. In order to be frequency selective, multiplying phase comparators are used to compare the source signal with the synthesized reference signal. Phase comparators of this sort produce an output with a mean value which is a function of the phase error. They also produce a dominant ac component which is the second harmonic of the source and may produce other ac components depending upon the nature of the input waveform.
In the normal working range, that is close to phase lock, the dc error is closely proportional to the actual phase error. When the reference wave leads the input by less than 90 degrees, the dc component becomes more positive. When the output leads by more than 90 degrees, the output will become negative. Phase lock is maintained because the integral of the phase error signal and the VCO frequency continue to change until the phase error is eliminated. Since the phase error signal from the phase comparator is predominantly second harmonic, and may contain some other frequency components if the input is distorted, a means to neutralize or attenuate these components is necessary to minimize harmonic modulation of the VCO frequency. A slow responding integrator or filters have been used to maintain the frequency modulation of the VCO to an acceptable low level However, these devices reduce the bandwidth of the phase locked loop circuit. As a result, the output is a compromise of response time and accuracy.
U.S. Pat. No. 4,669,024 discloses a three-phase phase locked loop circuit which individually multiplies each phase of the source by the corresponding phase of a three-phase reference signal. These three separate phase error signals are then summed to produce a total phase error signal which is integrated and applied to the VCO. As long as the three phases of the source signal are balanced, summing of the individual phase error signals results in cancellation of the major second harmonic ac components and the total phase error signal, thereby enabling the use of a faster slewing integrator and elimination of the filter. While the phase lock loop of U.S. Pat. No. 4,669,024 eliminates these ac components for ideal balanced three-phase inputs by summing the three-phase error signals from three identical phase comparators, in the case of unbalanced multiphase and single phase inputs, some second harmonic remains and a slow responding integrator or filter is still required to keep the frequency modulation of the VCO to an acceptably low level.
Accordingly, there is a need for a phase locked loop circuit without significant ripple in the phase error signal even with unbalanced three-phase and single phase inputs.
There is also a need for such a phase lock loop circuit which is easily and economically incorporated into present phase lock loop circuits.